Vhdl Based Test Generation System

DECIDER: A Decision Diagram Based Hierarchical Test Generation System

Current paper presents a hierarchical test pattern generation system that uses register-transfer level VHDL and gate-level EDIF netlist descriptions as inputs. The system includes appropriate interfaces to synthesize Decision Diagram (DD) models, a DD based test pattern generator and a fault simulator to evaluate the quality of the generated tests. In the paper, the structure of the system is p...

High level test bench generation using software engineering concepts

The tool to be presented in the panel deals with validation of VHDL descriptions at the early phase of the design of a digital system. Our approach consists in generating test data from a given VHDL behavioral description. The validation is achieved by comparing the results obtained using the simulation of the VHDL description within the test data and the results which should have been obtained...

Toward Automatic Test Pattern Generation for VHDL Descriptions

This paper describes an approach for defining a model for the VHDL descriptions which can be used for test generation purpose. The VHDL description can be transformed to this model by semantic preserving transformations without lost of information needed for test generation purpose. Together with the model definition a unified fault model is defined which can be easily related to well known fau...

VHDL Design of a Test Processor Based on Mixed-Mode Test Generation

Behavioral Modeling and Simulation of Semiconductor Devices and Circuits Using VHDL-AMS

During the past few years, a lot of work has been done on behavioral models and simulation tools. But a need for modeling strategy still remains. The VHDL-AMS language supports the description of analog electronic circuits using Ordinary Differential Algebraic Equations (ODAEs), in addition to its support for describing discrete-event systems. For VHDL-AMS to be useful to the analog design ...